--rundy 8
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity runda8 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end runda8;

architecture Behavioral of runda8 is
component keymix is 
    Port ( kid : in  STD_LOGIC_VECTOR (127 downto 0);
		kik : in STD_LOGIC_VECTOR (127 downto 0);
		ko : out  STD_LOGIC_VECTOR (127 downto 0));
end component keymix;

component Sbox7set is
    Port ( si : in  STD_LOGIC_VECTOR (127 downto 0);
		so : out  STD_LOGIC_VECTOR (127 downto 0));
end component Sbox7set;

component lineartransf is
    Port ( li : in  STD_LOGIC_VECTOR (127 downto 0);
		lo : out  STD_LOGIC_VECTOR (127 downto 0));
end component lineartransf;

signal n1, n2 : STD_LOGIC_VECTOR (127 downto 0);
begin
b1: keymix port map(ri,rk,n1);
b2: Sbox7set port map(n1,n2);
b3: lineartransf port map(n2,ro);
end Behavioral;